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lx1801 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 1 copyright ? 2005 rev. 1.1, 7/7/2006 www. microsemi . com smbus to analog & digital system interface tm ? descri pt i on the lx1801 is a smbus controlled dimming interface for ccfl inverters. it complies with the dell inc. m07 specification for notebook backlight inverters. the lx1801 processes 3 brightness control inputs, one each from the smbus, an ambient light sensor, and a separate system side pwm signal and generates an analog output signal that drives the dimming circuitry of a ccfl inverter controller. five different brightness control modes are supported which include intel dpst display power saving technology. in addition to its smbus interface, the lx1801 contains an eight bit adc, seven 8 bit registers, three 8 bit dacs, a multiplier, and other special circuits that process its analog voltage output. the lx1801 controls inverter on/off and monitors and reports lamp status and inverter faults in real time. the lx1801 is ava ilable in the 16 lead 3 x 3mm mlpq package. important: for the most current data, consult microsemi s website: http://www.microsemi.com k ey feat u r es ? fully compliant to standard smbus specifications ? i2c bus compatible ? 8 bit resolution ? 10 lsb accuracy ? one 8 bit adc ? three 8 bit dacs ? smbus address strap for 2 selectable addresses ? external reference inputs set analog brightness voltage lower limit and range appli c at i on s ? processor and ambient light senor (als) controlled lcd panel dimming with intel dpst ? general purpose smbus i/o control applications produ ct h i gh li gh t part als_in sda scl pwm_in vss ovr_cur lmp_on lmp_c vss flt_dly en_out brite_out adr0 v_bot vref_in vdd lx169x based ccfl inverter lx1801 notebook lcd inverter with 5 smbus dimming modes including bus driven, ambient light sensor dr iven, pwm driven, and either smbu s or als with intel ? dpst enhancement. i/o conn smb_dat smb_clk inv_pwm part lx1972 als 5v pack age order i n fo lq plastic 3x3 mm mlpq 16 pin t j ( c) rohs compliant / pb-free -40 to 85 lx1801ilq note: available in tape & reel. append the lett ers tr to the part num ber. (i.e. lx1801ilq-tr) l l x x 1 1 8 8 0 0 1 1 obsolete downloaded from: http:///
lx1801 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 2 copyright ? 2005 rev. 1.1, 7/7/2006 www. microsemi . com smbus to analog & digital system interface tm ? absolu t e m ax i m u m rat i n gs supply input voltage ........................................................................-0.3v to 7.0v input and output pi ns .......................................................................-0.3v to 7.0v operating temperature range. ...-40 to 85 c maximum operating junc tion temperat ure ................................................ 150 c storage temperat ure range...........................................................-65 c to 150 c peak package solder refl ow temp (40 seconds max. exposure)..... 260c(+0,-5) note: exceeding these ratings could cause damage to the device. all voltages are with respect to ground. currents are positive into, negative out of specified terminal . t h erm al dat a lq plastic 3x3 mm mlpq 16-pin thermal resistance - junction to a mbient , ja 33.3 c/w junction temperature calculation: t j = t a + (p d x ja ). the ja numbers are guidelines for the thermal performan ce of the device/pc-board system. all of the above assume no ambient airflow. pack age pi n ou t als_in 12 3 4 567 8 9 10 11 12 13 14 15 16 sda scl pwm_in vss ovr_cur lmp_on lmp_c brite_out en_out flt_dly vss vdd vref_in v_bot adr0 lq p ackage (top view) rohs / pb-free 100% matte tin lead finish p p a a c c k k a a g g e e d d a a t t a a obsolete downloaded from: http:///
lx1801 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 3 copyright ? 2005 rev. 1.1, 7/7/2006 www. microsemi . com smbus to analog & digital system interface tm ? fu n ct i on al pi n descri pt i on name description vdd power supply input: 4.5v to 5.5v vss ground (2 pins) scl digital input. smbus clock C 10 to 100 khz capable sda digital i/o. smbus data C smbus data line adr0 smbus address strap input C the address for the lx1801 is determined by the state of this pin (see table 1). als_in analog input. ambient light sensor input. zero to vref_in range. pwm_in a digital input from the system controller whose dut y cycle determines lamp brightness when in pwm mode, and multiplies lamp brightness by a fractional value equal to its duty cycle when in dpst mode. vref_in analog input reference voltage for adc and dac. operating range is 1.5 to 3 vdc. nominal input is 2.040v. input impedance is greater than 10m ? . v_bot an analog voltage input whose value determines the mi nimum output voltage of brite_out after the effect of the pwm input when in dpst mode and at all times in other modes. brite_out analog output voltage that is equal to desired brit e_out voltage after modulation by the pwm input and offset by the voltage at the v_bot inpu t. an r/c filter at this pin to lo w pass filters the signal and determines response time when in pwm and dpst modes. in pw m and dpst modes, the output voltage is modulated on and off at the duty cycle and frequency of pwm_in. the r/c filter is comprised of an internal 100k resistor and an external capacitor to ground. lmp_c lamp capacitor. a capacitor, typica lly 10nf and a resistor, typically 1m ? , are connected in parallel from this pin to ground. they filter a peak voltage detector with the lmp_on input. ovr_cur analog / digital input to comparator and latch. used fo r over current status input in m07 application. 1.2v threshold. if ovr_cur > 1.2v dc , a 1 is latched and written to bit 0 (fault) and bit 2(ov_curr) of the fault status register (register 0x 02). the latched bits can only be cleared by a write byte command to register 0x01 to make the lamp_ctl bit true. if bit 0 or bit 2 of register 0x02 is set, this will reset the lamp_ctl bit in register 0x01, causing the enable out put to the ccfl controller (en_out) to go low and turn off the inverter. zero to vdd input voltage range. lmp_on digital input. approximately 1v threshold. when lm p_on is 1 it charges the capacitor at pin lmp_c to vdd, indicating the lamp is turned on. this pin is normally connected to the a_out pin of the lx1692 / 93 controller, and will cause internal circuitry to report t he lamp is on if there are pulses on a_out. if these pulses stop long enough for the voltage at lmp_c to dec rease below 1.2 v, the lamp is reported off at bit 03 of the flt/stat register (0x02). . if lamp_ctl tr ansitions to high, requesting the inverter to turn on, and lmp_c does not go above 1.2v before the flt_dly pin reaches 2.5v, an open lamp error signal is produced and is stored, along with other error conditions, to bit zero of the flt status register 0x02. an open lamp fault will cause en_out to go low. see flt_dly description. zero to vdd input voltage range flt_dly analog / digital input to the open lamp comparator and latch. this input provides for a time out before lmp_on is sensed for an open lamp fault. the comparator has a 2.5v threshold. the comparator output is latched when 2.5v is exceeded. the latch is reset at power on and when en_out transitions to high. this pin is normally connected to the c_to pin of the lx1692 or 1693 ccfl controller. en_out digital output. enable output to ccfl controller. ttl voltage and current levels. en_out is made high or low by a write byte command to register 0x01. it is also reset by bit zero of register 0x02 going high. p p a a c c k k a a g g e e d d a a t t a a obsolete downloaded from: http:///
lx1801 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 4 copyright ? 2005 rev. 1.1, 7/7/2006 www. microsemi . com smbus to analog & digital system interface tm ? elect ri cal ch a ract eri st i cs unless otherwise specified, the following specifications apply over the operating ambient temperature -40 c t a 85 c except where otherwise noted and the following test conditions: v dd = 5v + 10 / -5%. lx1801 parameter symbol test conditions min typ max units ` power supply operating supply voltage vdd 4.5 5.5 v average supply current idd dac = ffh; idle adc 1.0 2.5 4.0 ma ` brightness control dac dc performance resolution 8 bits integral nonlinearity inl code = 0 to 255, -10na < iout < 10na -9 9 lsb differential nonlinearity dnl code = 0 to 255, -10na < iout < 10na -2 5 lsb full scale output voltage fsv code = 255, -10na < iout < 10na 97% * vref vref 103% * vref v offset error code = 0, -10na < iout < 10na -3 4 lsb gain error -10na < iout < 10na -4 2 3 % of ideal ` low limit clamp dac dc performance resolution 8 bits relative accuracy (note 1) low limit dac code = 15 to 205, high limit dac code > 50 lsb above low limit dac code -10 7 lsb offset error low limit dac code = 0, high limit dac code > 50 lsb above low limit dac code -1 12 lsb ` high limit clamp dac dc performance resolution 8 bits relative accuracy (note 2) high limit dac code = 50 to 232, low limit dac code = 50 lsb below high limit dac code -7 7 lsb ` als mode accuracy output error at brite_out low limit dac code = 15 to 205, high limit dac code > 50 lsb above low limit dac code, als_in = 20% * vref to 80% * vref. vbot = 0v 3 % of als_in ` adc resolution 8 bits resolvable input range 0 vref v full scale output voltage fsv 97% * vref vref 103% * vref v input leakage current (als_in) i_leak als_in = 0v to vdd -1 +1 a integral nonlinearity inl only major carry codes tested 3 lsb differential nonlinearity dnl only major carry codes tested 1.5 lsb offset error als_in = 0v -2 0 2 lsb gain error als_in = vref; read register. 4 -3 2 3 % of fsr ` ref_in reference voltage v ref 1.80 2.040 3.00 v input leakage current i ref -50 0 50 na ` adr high level input voltage v ahl 80 %vdd low level input voltage v all 20 %vdd input leakage current i adr -50 0 50 na ` scl, sda, pwm high level input voltage v shl 2.1 v low level input voltage v sll 0.8 v input leakage current i smb -5 0 1 a sda low level output voltage v ol iout = 3ma 0.4 v ` smbus smb clock frequency f clk 10 100 khz note 1: the relative accuracy of the lo w limit dac is specified to be the deviati on from the ideal programmed value: ideal = v ref * (code/255). the relative accuracy is specified for the range code = 15 to 205 note 2: the relative accuracy of the high limit dac is specifi ed to be the deviation from the ideal programmed value: ideal = vref * (code/255). the relative accuracy is specified for the range code = 50 to 232 e e l l e e c c t t r r i i c c a a l l s s obsolete downloaded from: http:///
lx1801 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 5 copyright ? 2005 rev. 1.1, 7/7/2006 www. microsemi . com smbus to analog & digital system interface tm ? appli cat i on n ot e the lx1801 is a seven register device that uses smbus commands to communicate with the host system. all registers are defined as full byte wide with rese rved (undefined) bits containing a default value of 0. four of the seven registers are read / write, and three are read only with respect to the smbus. smb protocol only standard smbus protocol, version 2.0 or higher, may be used for this device. the only required commands are the smbus read byte and the smbus write byte protocols. there are to be no non standard protocols impl emented. further, register contents shall not be altered by invalid commands. general rules for writing and r eading lx1801 registers with the smbus. writes to registers can be performed by either the smbus write byte protocol and / or by internal ic logic, depending on the register type (see table 1). reads can be performed on all seven registers by issuing the read_byte protocol. read only registers can be written only by internal logic. their contents can not be affected by smbus write commands. specific requirements for smbus protocols: ? the ic shall implement the smbus read byte protocol. ? the ic shall implement the smbus write byte protocol. ? the ic shall not require the use of any other smbus protocol to meet the requirements contained in the dell m07 specification. ? the ic shall operate correctly when the smbus master clock operates at a frequency of 55 khz and over the complete frequency range of 10khz to 100khz. ? the ic shall not employ clock stretching. ? the ic shall not include smbus pull up resistors. these are provided by the host system. read byte protocol: s slave address wr a command code a s slave address rd a data byte p 1 7 1 1 8 1 1 7 1 1 8 1 1 write byte protocol: s slave address wr a command code a data byte p 1 7 1 1 8 1 8 1 1 grey shading represents cycles during which the lx1801 owns or d rives the data line. all other cycles are driven by the ho st. definitions s: start condition wr: write rd: read a: acknowledge p: stop condition protocol must be per standard smb specification version 2.0 or higher. a a p p p p l l i i c c a a t t i i o o n n s s obsolete downloaded from: http:///
lx1801 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 6 copyright ? 2005 rev. 1.1, 7/7/2006 www. microsemi . com smbus to analog & digital system interface tm ? appli cat i on n ot e smbus de-featuring packet error correction (pec) and th e alarm function are not supported. device address: in this document the device address is al ways expressed as a full 8 bit address. the high nibble of the address is always 5h. in the low nibble bit 0 is always the r/w bit, and bits 3-1 are a2, a1, and a0. th is device implements one address strap at a0. when this strap is grounded the resulting device address is 58(h); when pulled to 5v, the resu lting device address is 5a(h). the state of the a0 strap is sensed at power on reset. the pin will not change state when the system is in operation. register definitions: bit definitions description addr type 7 6 5 4 3 2 1 0 brightness control 0x00 r/w brt7 brt6 brt5 br t4 brt3 brt2 brt1 brt0 device control 0x01 r/w resrv d resrvd als dly1 (option) als dly0 (option) als_ctl pwm_md pwm_sel lmp_ctl fault / status 0x02 r/o resr vd resrvd resrvd resrvd lmp_st 1= lamp is on ov_cur 1= over curent thr_sd 1= over temp fault 1= any fault identification 0x03 r/o mfg4 mfg3 mfg2 mfg1 mfg0 rev2 rev1 rev0 als status 0x04 r/o als7 als6 al s5 als4 als3 als2 als1 als0 als low limit 0x05 r/w alsll7 alsll6 alsll5 alsll4 alsll3 alsll2 alsll1 alsll0 als high limit 0x06 r/w alshl7 alshl6 alshl5 alshl4 alshl3 alshl2 alshl1 alshl0 specific requirements for register 0: 1. a write byte cycle shall set the brightness level if the ic is in smbus mode as selected by bits 3-1 of the device control regi ster. 2. a write byte cycle shall have no effect on the brite_out pin when the ic is not in the smbus mode. 3. a read byte cycle shall return the current brightness level regardless of the value of pwm_sel. 4. when in smbus or smbus + dpst mode, register 0x00 must reflect exactly the last value written to it via the smbus, not a digitized version of the analog br ightness control output voltage. if dpst is active a read to register 0x00 shall not include its affect. 5. when the pwm or als or als+dpst mode is set, register 0x00 reads will return th e digitized dc brightness control voltage exclusive of any offset produced from the v_bot input. range of the read voltage is from zero to vref_in. 6. a value of 0xff shall set the brite_ out level to maxi mum brightness. 7. a value of 0x00 shall set the brite_ out level to mini mum brightness. 8. the default value shall be 0xff. specific requirements for register 4: 1. register 0x04 reads always produce the digitized raw als_in voltage, independent of what mode has b een set. this data will not include the effect of dpst if dpst is active, or the effect of the high and low limit registers. a a p p p p l l i i c c a a t t i i o o n n s s obsolete downloaded from: http:///
lx1801 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 7 copyright ? 2005 rev. 1.1, 7/7/2006 www. microsemi . com smbus to analog & digital system interface tm ? lx 1 8 0 1 com m an ds w/r register description w 0x00 write an 8 bit data byte to the brightness control register. r 0x00 read the 8 bit data byte stored in the brightness control register. w 0x01 write an 8 bit control byte to the device control register. see the m07 specification for command details. r 0x01 read the 8 bit control byte from the device control register. see the m07 specification for command details. w 0x02 write the 8 bit fault / status register. this register shall ignore writ e operations. it is read only. r 0x02 read the 8 bit fault / status register. see the m07 specification for command details. w 0x03 write the 8 bit identif ication register. this register shall ignore writ e operations. it is read only. r 0x03 read the 8 bit identif ication register. see the m07 specification for command details. w 0x04 write the 8 bit als status register. this register shall ignore writ e operations. it is read only. r 0x04 read the 8 bit als status register. see the m07 specification for command details. w 0x05 write the 8 bit als low limit register. see the m07 specification for command details. r 0x05 read the 8 bit als low limit register. see the m07 specification for command details. w 0x06 write the 8 bit als high limit register. see the m07 specification for command details. r 0x06 read the 8 bit als high limit register. see the m07 specification for command details. a a p p p p l l i i c c a a t t i i o o n n s s obsolete downloaded from: http:///
lx1801 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 8 copyright ? 2005 rev. 1.1, 7/7/2006 www. microsemi . com smbus to analog & digital system interface tm ? fu n ct i on al block di agram lx1801 functional block diagram revision x2 k 3 november 05 microsemi integrated products pwm_md adc als 0x04 vss2 ovr_cur flt/ stat latch 0x02 1p2v lmp_on vss1 lx1972 als-in vdd c1 als r1 20.0k 5v dac dac als low 0x05 als high 0x06 v_refv_ref - + v_ref + - smbus control sda adr0 id/ rev 0x03 als_ctl pwm_md pwm_sel lamp_ctl dvc ctl 0x01 en_out flt-dly pwm_in pwm_sel 0 1 2 3 vref_in dac a mux por brite 0x00 lamp_ctrlposedge als dly (n/u) als dly (n/u) 5vdc als_ctl 2p5v v_ref pwm_sel 1 0 rd_als als_ctl opn lmp rst_ lamp_ ctl smdata rst o/s + - r4 10k a mux 1 0 a mux 1 0 v_ref 5vdc + - 100k scl v_bot vdd_a r3 30k r2 40k + - 5vdc brite_out c2 100nf 5vdc brite_out + - 100k smbus v_ref c3 10 nf - + 200mv lamp_stat ov_curr fault thrm_shdn r5 1m - + r s q 5v lmp_c 100k 100k figure 1 C block diagram a a p p p p l l i i c c a a t t i i o o n n s s obsolete downloaded from: http:///
lx1801 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 9 copyright ? 2005 rev. 1.1, 7/7/2006 www. microsemi . com smbus to analog & digital system interface tm ? appli cat i on ci rcu i t s lx1692 wide input voltage range notebook inverter with als & intel dpst for dell m07 inverters lx1801 application schematic with lx1962 rev 4nov05.vsd 10uf jst smo2 als lx1972 gnd inv_src inv_pwm 5valw smb_clk smb_dat 5valw g2p 1 s2p 23 g1n d2p s1n d1n 65 4 fdc6333c vdda 1 c_r 23 c_bst 4 c_to vddp aout bout gnd 2019 18 17 lx1692 brite_a 7 vin_sns 89 brite_d 10 vcomp i_sns ov_sns icomp oc_sns 1413 12 11 i_r 5 cout 16 enable 6 dout 15 vdda inv_src 5valw 5valw 40 components g2p 1 s2p 23 g1n d2p s1n d1n 65 4 fdc6333c adr0 1 scl 23 scd 4 pwm_in vdd brite_out vss2 en_out 1615 14 13 lx1801 vref_in 5 v_bot 67 als_in 8 vss1 flt_dly lmp_on lmp_c ovr_cur 1211 10 9 figure 2 C typical application a a p p p p l l i i c c a a t t i i o o n n s s obsolete downloaded from: http:///
lx1801 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 10 copyright ? 2005 rev. 1.1, 7/7/2006 www. microsemi . com smbus to analog & digital system interface tm ? t h eory of o perat i on b asic f unctionality the lx1801 contains three 8 bit dacs, an 8 bit adc and a smbus interface with 7 addressabl e registers to control 5 dimming modes for a notebook backlight inverter. the adc contains a track and hold input that stores the analog voltage level while the conversion is being processed. se veral special circuits are also present in the lx1801. analog comparators and a 2 bit r/s register detect and latch inverter fault conditions. another analog comparator monitors real time on / off status of the ccfl lamp and writes it, along with inverter fault status to a host readable register. an analog multiplier provides the ability for implementing intel tm dpst (display power savings t echnology), and voltage limiting clamps on the als input provi de smbus programmable range limiting of the ambient light sensor output signal. smb us i nterface the lx1801 communicates over the smbus in the slow speed low power level and operates in a slave mode receiving commands and sending and receivi ng data from the host or bus master. the lx1801 can be configured for one of two addresses by connecting the adr0 input to 5v or ground. addresses 0x58 and 0x5a can be selected with the strapping code below: table 1. address strapping codes option # adr 0 hex address 1 0v :058 2 5v :05a appli cat i on n ot e l ayout g uidelines the lx1801 is sensitive to noise at the analog input pins so these nodes should be a low impedance path to ground for high frequency noise. as a precaution, the brite_out and als _in pins should be routed away from digital sw itching traces and have ceramic capacitors located close to the pa ckage pins. the vdd pin should be decoupled to ground with a 0.1uf cer amic capacitor located as close as possible to the ic. a a p p p p l l i i c c a a t t i i o o n n s s obsolete downloaded from: http:///
lx1801 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 11 copyright ? 2005 rev. 1.1, 7/7/2006 www. microsemi . com smbus to analog & digital system interface tm ? pack age di m en si on s lq 16-pin mlpq 3x3 e d e b e2 d2 a a3 a1 l k pin 1 i ndicat or or m illimeters i nches dim min max min max a 0.80 1.00 0.031 0.039 a1 0 0.05 0 0.002 a3 0.20 ref 0.008 ref b 0.18 0.30 0.007 0.012 d 3.00 bsc 0.118 bsc e 3.00 bsc 0.118 bsc e 0.50 bsc 0.020 bsc d2 1.30 1.55 0.051 0.061 e2 1.30 1.55 0.051 0.061 k 0.2 - 0.008 - l 0.35 0.50 0.012 0.020 l1 - 0.15 - 0.006 note: 1. dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(.006) on any side. lead dimension shall not include solder coverage. 2. due to multiple qualified assembly sub-contractors either package (with different pin one indicators) may be shipped. package type will be consistent within the smallest individual container. m m e e c c h h a a n n i i c c a a l l s s obsolete downloaded from: http:///
lx1801 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 12 copyright ? 2005 rev. 1.1, 7/7/2006 www. microsemi . com smbus to analog & digital system interface tm ? n ot es production data C information contained in this document is proprietary to microsemi and is current as of publication date. this document may not be modified in any way without the express written consent of microsemi. product processing does not necessarily include testing of all parameters. microsemi reserves th e right to change the configuration and performance of the product and to discontinue product at any time. n n o o t t e e s s obsolete downloaded from: http:///

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